Arbitrating circuit

ABSTRACT

An arbitrating circuit includes a first NOR gate, a second NOR gate, four resistors and a pull-up circuit. The first transistor is connected with the first node and the second node, and generates a first acknowledging signal. The second transistor is connected with a supply voltage, the second node and the first transistor. The third transistor is connected with the first node and second node, and generates a second acknowledging signal. The fourth transistor is connected with the supply voltage, the first node and the third transistor. The pull-up circuit is connected with the first node, the second node, the first NOR gate and the second NOR gate. If both of the first request signal and the second request signal have a low logic level, a voltage at the second node is pulled up to a high logic level by the pull-up circuit.

This application claims the benefit of People's Republic of China PatentApplication No. 201710866229.7, filed Sep. 22, 2017, the subject matterof which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to an electronic circuit, and moreparticularly to an asynchronous arbitrating circuit.

BACKGROUND OF THE INVENTION

An arbitrating circuit is important for designing a logic circuit. Thearbitrating circuit receives plural request signals and determines thepriorities of the request signals according to the sequence of therequest signals.

For example, in case that a circuit system comprises plural controllersto access the memory, the circuit system has to be equipped with anarbitrating circuit. When the plural controllers issue read commands,the arbitrating circuit determines which controller is acknowledged tohave the priority to read the data from the memory according to thesequence of the read commands. In addition, the other controllers arenot acknowledged to read the data from the memory.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides an arbitrating circuit.The arbitrating circuit includes a first NOR gate, a second NOR gate, afirst transistor, a second transistor, a third transistor, a fourthtransistor and a pull-up circuit. A first input terminal of the firstNOR gate receives a first request signal. A second input terminal of thefirst NOR gate is connected with a first node. An output terminal of thefirst NOR gate is connected with a second node. A first input terminalof the second NOR gate receives a second request signal. A second inputterminal of the second NOR gate is connected with the second node. Anoutput terminal of the second NOR gate is connected with the first node.A source terminal of the first transistor is connected with the firstnode. A gate terminal of the first transistor is connected with thesecond node. A drain terminal of the first transistor generates a firstacknowledging signal. A source terminal of the second transistor isconnected with a supply voltage. A gate terminal of the secondtransistor is connected with the second node. A drain terminal of thesecond transistor is connected with the drain terminal of the firsttransistor. A source terminal of the third transistor is connected withthe second node. A gate terminal of the third transistor is connectedwith the first node. A drain terminal of the third transistor generatesa second acknowledging signal. A source terminal of the fourthtransistor is connected with the supply voltage. A gate terminal of thefourth transistor is connected with the first node. A drain terminal ofthe fourth transistor is connected with the drain terminal of the thirdtransistor. The pull-up circuit is connected with the first node, thesecond node, the first input terminal of the first NOR gate and thefirst input terminal of the second NOR gate. If both of the firstrequest signal and the second request signal have a low logic level, avoltage at the second node is pulled up to a high logic level by thepull-up circuit.

Another embodiment of the present invention provides an arbitratingcircuit. The arbitrating circuit includes a first NAND gate, a secondNAND gate, a first transistor, a second transistor, a third transistor,a fourth transistor and a pull-down circuit. A first input terminal ofthe first NAND gate receives a first request signal. A second inputterminal of the first NAND gate is connected with a first node. Anoutput terminal of the first NAND gate is connected with a second node.A first input terminal of the second NAND gate receives a second requestsignal. A second input terminal of the second NAND gate is connectedwith the second node. An output terminal of the second NAND gate isconnected with the first node. A source terminal of the first transistoris connected with the first node. A gate terminal of the firsttransistor is connected with the second node. A drain terminal of thefirst transistor generates a first acknowledging signal. A sourceterminal of the second transistor is connected with a ground terminal. Agate terminal of the second transistor is connected with the secondnode. A drain terminal of the second transistor is connected with thedrain terminal of the first transistor. A source terminal of the thirdtransistor is connected with the second node. A gate terminal of thethird transistor is connected with the first node. A drain terminal ofthe third transistor generates a second acknowledging signal. A sourceterminal of the fourth transistor is connected with the ground terminal.A gate terminal of the fourth transistor is connected with the firstnode. A drain terminal of the fourth transistor is connected with thedrain terminal of the third transistor. A pull-down circuit is connectedwith the first node, the second node, the first input terminal of thefirst NAND gate and the first input terminal of the second NAND gate. Ifboth of the first request signal and the second request signal have ahigh logic level, a voltage at the second node is pulled down to a lowlogic level by the pull-down circuit.

Numerous objects, features and advantages of the present invention willbe readily apparent upon a reading of the following detailed descriptionof embodiments of the present invention when taken in conjunction withthe accompanying drawings. However, the drawings employed herein are forthe purpose of descriptions and should not be regarded as limiting.

BRIEF DESCRIPTION OF THE DRAWINGS

The above objects and advantages of the present invention will becomemore readily apparent to those ordinarily skilled in the art afterreviewing the following detailed description and accompanying drawings,in which:

FIG. 1A is a schematic circuit diagram illustrating an arbitratingcircuit according to a first embodiment of the present invention;

FIG. 1B is a schematic timing waveform diagram illustrating associatedsignals of the arbitrating circuit of FIG. 1A;

FIG. 2A is a schematic circuit diagram illustrating an arbitratingcircuit according to a second embodiment of the present invention;

FIG. 2B is a schematic circuit diagram illustrating an exemplary pull-upcircuit used in the arbitrating circuit of FIG. 2A;

FIG. 2C is a schematic circuit diagram illustrating another exemplarypull-up circuit used in the arbitrating circuit of FIG. 2A;

FIG. 2D is a schematic timing waveform diagram illustrating associatedsignals of the arbitrating circuit of FIG. 2A;

FIG. 3A is a schematic circuit diagram illustrating an arbitratingcircuit according to a third embodiment of the present invention;

FIG. 3B is a schematic circuit diagram illustrating an exemplarypull-down circuit used in the arbitrating circuit of FIG. 3A;

FIG. 3C is a schematic circuit diagram illustrating another exemplarypull-down circuit used in the arbitrating circuit of FIG. 3A; and

FIG. 3D is a schematic timing waveform diagram illustrating associatedsignals of the arbitrating circuit of FIG. 3A.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1A is a schematic circuit diagram illustrating an arbitratingcircuit according to a first embodiment of the present invention. FIG.1B is a schematic timing waveform diagram illustrating associatedsignals of the arbitrating circuit of FIG. 1A. The arbitrating circuit10 comprises a first NOR gate 12, a second NOR gate 14, and fourtransistors m1˜m4. The transistors m1 and m3 are N-type transistors. Thetransistors m2 and m4 are P-type transistors.

A first input terminal of the first NOR gate 12 receives a requestsignal REQa. A second input terminal of the first NOR gate 12 isconnected with a node “b”. An output terminal of the first NOR gate 12is connected with a node “a”. A first input terminal of the second NORgate 14 receives a request signal REQb. A second input terminal of thesecond NOR gate 14 is connected with the node “a”. An output terminal ofthe second NOR gate 14 is connected with the node “b”.

The source terminal of the transistor m1 is connected with the node “b”.The gate terminal of the transistor m1 is connected with the node “a”.The drain terminal of the transistor m1 generates an acknowledgingsignal ACKa. The source terminal of the transistor m2 receives a supplyvoltage Vcc. The gate terminal of the transistor m2 is connected withthe node “a”. The drain terminal of the transistor m2 is connected withthe drain terminal of the transistor m1. The voltage of the high logiclevel is equal to the supply voltage Vcc. The voltage of the low logiclevel is equal to 0V.

The source terminal of the transistor m3 is connected with the node “a”.The gate terminal of the transistor m3 is connected with the node “b”.The drain terminal of the transistor m3 generates an acknowledgingsignal ACKb. The source terminal of the transistor m4 receives thesupply voltage Vcc. The gate terminal of the transistor m4 is connectedwith the node “b”. The drain terminal of the transistor m4 is connectedwith the drain terminal of the transistor m2.

In this embodiment, the low logic level (i.e., 0V) indicates that thesignal is activated, and the high level (i.e., Vcc) indicates that thesignal is inactivated.

In case that the request signals REQa and REQb are both inactivated, thevoltages at the node “a” and the node “b” have the low logic level(i.e., 0V). The transistors m2 and m4 are turned on. The transistors m1and m3 are turned off. Consequently, the acknowledging signals ACKa andACKb are inactivated (i.e., Vcc).

In case that the request signal REQa is activated (i.e., 0V) and therequest signal REQb is inactivated (i.e., Vcc), the voltage at the node“a” has the high logic level (i.e., Vcc) and the voltage at the node “b”has the low logic level (i.e., 0V). The transistors m1 and m4 are turnedon. The transistors m2 and m3 are turned off. Consequently, theacknowledging signal ACKa is activated (i.e., 0V), and the acknowledgingsignal ACKb is inactivated (i.e., Vcc).

In case that the request signal REQa is inactivated (i.e., Vcc) and therequest signal REQb is activated (i.e., 0V), the voltage at the node “a”has the low logic level (i.e., 0V) and the voltage at the node “b” hasthe high logic level (i.e., Vcc). The transistors m2 and m3 are turnedon. The transistors m1 and m4 are turned off. Consequently, theacknowledging signal ACKa is inactivated (i.e., Vcc), and theacknowledging signal ACKb is activated (i.e., 0V).

As mentioned above, the arbitrating circuit 10 is capable of determiningwhether the acknowledging signal ACKa or the acknowledging signal ACKbis activated. If the request signal REQa is activated earlier, theacknowledging signal ACKa is activated and the acknowledging signal ACKbis inactivated. Whereas, if the request signal REQb is activatedearlier, the acknowledging signal ACKb is activated and theacknowledging signal ACKa is inactivated.

However, if the request signals REQa and REQb are activatedsimultaneously, the acknowledging signal ACKa or the acknowledgingsignal ACKb generated by the arbitrating circuit 10 is unexpected. Thereasons will be described as follows.

Please refer to FIG. 1B. At the time point ta, the request signals REQaand REQb are activated simultaneously (i.e., 0V). Meanwhile, thearbitrating circuit 10 is in a metastable state (MS).

In the metastable state, the voltages at the node “a” and the node “b”are in the range between the high logic level and the low logic level.At the time point tb, the arbitrating circuit 10 is not in themetastable state. Meanwhile, the voltage at the node “b” is decreased tothe low logic level (i.e., 0V) and the voltage at the node “a” isincreased to the high logic level (i.e., Vcc). Consequently, theacknowledging signal ACKa is activated (i.e., 0V), and the acknowledgingsignal ACKb is inactivated (i.e., Vcc).

Generally, the first NOR gate 12, a second NOR gate 14 and thetransistors m1˜m4 have different driving capabilities. Due to thedifferences of the driving capabilities, the arbitrating circuit 10generates different results. That is, if the request signals REQa andREQb are activated simultaneously, the time duration of maintaining thearbitrating circuit in the metastable state is different and unexpected.

In some situations, the request signals REQa and REQb are activatedsimultaneously, but the acknowledging signal is different. For example,the voltage at the node “b” is increased to the high logic level and thevoltage at the node “a” is decreased to the low logic level.Consequently, the acknowledging signal ACKa is inactivated, and theacknowledging signal ACKb is activated.

That is, if the request signals REQa and REQb are activatedsimultaneously, the result of the arbitrating circuit 10 is unexpected.

FIG. 2A is a schematic circuit diagram illustrating an arbitratingcircuit according to a second embodiment of the present invention. FIG.2B is a schematic circuit diagram illustrating an exemplary pull-upcircuit used in the arbitrating circuit of FIG. 2A. FIG. 2C is aschematic circuit diagram illustrating another exemplary pull-up circuitused in the arbitrating circuit of FIG. 2A. FIG. 2D is a schematictiming waveform diagram illustrating associated signals of thearbitrating circuit of FIG. 2A.

As shown in FIG. 2A, the arbitrating circuit 20 comprises a first NORgate 12, a second NOR gate 14, four transistors m1˜m4 and a pull-upcircuit 16.

In comparison with the first embodiment, the arbitrating circuit 20 ofthis embodiment further comprises the pull-up circuit 16. The pull-upcircuit 16 is connected between the supply voltage Vcc and the node “a”.The relationships between the other components of the arbitratingcircuit 20 are similar to those of the first embodiment, and are notredundantly described herein.

In this embodiment, the pull-up circuit 16 is connected with the node“a”, the node “b”, the first input terminal of the first NOR gate 12 andthe first input terminal of the second NOR gate 14. The pull-up circuit16 is operated according to the voltage at the node “a”, the voltage atthe node “b”, the request signal REQa and the request signal REQb. Incase that both of the request signals REQa and REQb have the low logiclevel, the pull-up path of the pull-up circuit 16 is temporarily turnedon. Under this circumstance, the voltage at the node “a” is pulled up tothe supply voltage Vcc.

In the example of FIG. 2B, the pull-up circuit 16 comprises fourtransistors, which are connected between the node “a” and the supplyvoltage Vcc in series. The gate terminals of the four transistors areconnected with the node “a”, the node “b”, the first input terminal ofthe first NOR gate 12 and the first input terminal of the second NORgate 14, respectively.

Please refer to FIG. 2B again. The pull-up circuit 16 comprises the fourtransistors ma, mb, mc and md. The transistors ma, mb, mc and md areserially connected between the node “a” and the supply voltage Vcc todefine the pull-up path. The transistors ma, mb, mc and md are P-typetransistors. The drain terminal and the gate terminal of the transistormd are connected with the node “a”. The drain terminal of the transistormc is connected with the source terminal of the transistor md. The gateterminal of the transistor mc is connected with the node “b”. The drainterminal of the transistor mb is connected with the source terminal ofthe transistor mc. The gate terminal of the transistor mb receives therequest signal REQb. The drain terminal of the transistor ma isconnected with the source terminal of the transistor mb. The gateterminal of the transistor ma receives the request signal REQa. Thesource terminal of the transistor ma is connected with the supplyvoltage Vcc.

It is noted that the signals to be received by the four gate terminalsof the pull-up circuit 16 may be varied according to the practicalrequirements. For example, in another embodiment, the gate terminals ofthe transistors md, mc, mb and ma are connected with node “b”, the node“a”, the request signal REQa and the request signal REQb, respectively.

In the example of FIG. 2C, the pull-up circuit 16 comprises an OR gate18 and three transistors. The two input terminals of the OR gate 18receive the request signals REQa and REQb, respectively. The threetransistors are connected between the node “a” and the supply voltageVcc in series. The gate terminals of the three transistors are connectedwith the node “a”, the node “b” and the output terminal of the OR gate18, respectively.

Please refer to FIG. 2C again. The pull-up circuit 16 comprises thethree transistors me, mf and mg and the OR gate 18. The transistors me,mf and mg are serially connected between the node “a” and the supplyvoltage Vcc to define the pull-up path. The transistors me, mf and mgare P-type transistors. The drain terminal and the gate terminal of thetransistor mg are connected with the node “a”. The drain terminal of thetransistor mf is connected with the source terminal of the transistormg. The gate terminal of the transistor mf is connected with the node“b”. The drain terminal of the transistor me is connected with thesource terminal of the transistor mf. The source terminal of thetransistor me is connected with the supply voltage Vcc. The two inputterminals of the OR gate 18 receive the request signals REQa and REQb.The output terminal of the OR gate 18 is connected with the gateterminal of the transistor me.

It is noted that the signals to be received by the three gate terminalsof the pull-up circuit 16 may be varied according to the practicalrequirements. For example, in another embodiment, the gate terminals ofthe transistors mg, mf and me are connected with node “b”, the node “a”and the output terminal of the OR gate 18, respectively.

The examples of the pull-up circuit 16 as shown in FIGS. 2B and 2C arepresented herein for purpose of illustration and description only. It isapparent to those ordinarily skilled in the art that numerousmodifications and alterations may be made while retaining the teachingsof the invention.

Similarly, the low logic level (i.e., 0V) indicates that the signal isactivated, and the high level (i.e., Vcc) indicates that the signal isinactivated.

In case that the request signals REQa and REQb are both inactivated(i.e., Vcc), the voltages at the node “a” and the node “b” have the lowlogic level (i.e., 0V). The transistors m2 and m4 are turned on. Thetransistors m1 and m3 are turned off. That is, the pull-up path of thepull-up circuit 16 is turned off. Consequently, the acknowledgingsignals ACKa and ACKb are inactivated (i.e., Vcc).

In case that the request signal REQa is activated (i.e., 0V) and therequest signal REQb is inactivated (i.e., Vcc), the voltage at the node“a” has the high logic level (i.e., Vcc) and the voltage at the node “b”has the low logic level (i.e., 0V). The transistors m1 and m4 are turnedon. The transistors m2 and m3 are turned off. That is, the pull-up pathof the pull-up circuit 16 is turned off. Consequently, the acknowledgingsignal ACKa is activated (i.e., 0V), and the acknowledging signal ACKbis inactivated (i.e., Vcc).

In case that the request signal REQa is inactivated (i.e., Vcc) and therequest signal REQb is activated (i.e., 0V), the voltage at the node “a”has the low logic level (i.e., 0V) and the voltage at the node “b” hasthe high logic level (i.e., Vcc). The transistors m2 and m3 are turnedon. The transistors m1 and m4 are turned off. That is, the pull-up pathof the pull-up circuit 16 is turned off. Consequently, the acknowledgingsignal ACKa is inactivated (i.e., Vcc), and the acknowledging signalACKb is activated (i.e., 0V).

As mentioned above, the arbitrating circuit 20 is capable of determiningwhether the acknowledging signal ACKa or the acknowledging signal ACKbis activated. If the request signal REQa is activated earlier, theacknowledging signal ACKa is activated and the acknowledging signal ACKbis inactivated. Whereas, if the request signal REQb is activatedearlier, the acknowledging signal ACKb is activated and theacknowledging signal ACKa is inactivated. Moreover, if the requestsignals REQa and REQb are not simultaneously activated, the pull-up pathof the pull-up circuit 16 is turned off.

In this embodiment, if the request signals REQa and REQb of thearbitrating circuit 20 are activated simultaneously, the acknowledgingsignal ACKa is activated, and the acknowledging signal ACKb isinactivated. The reasons will be described as follows in more details.

Please refer to FIG. 2D. At the time point tc, the request signals REQaand REQb are activated simultaneously (i.e., 0V). Meanwhile, thearbitrating circuit 20 is in a metastable state (MS).

In the metastable state, the request signals REQa and REQb have the lowlogic level (i.e., 0V), and the voltages at the node “a” and the node“b” are in the range between the high logic level and the low logiclevel. Consequently, the transistors ma, mb, mc and of the pull-upcircuit 16 as shown in FIG. 2B are turned on. That is, the pull-up pathof the pull-up circuit 16 is turned on. Similarly, in the metastablestate, the transistors me, mf and mg of the pull-up circuit 16 as shownin FIG. 2C are turned on. That is, the pull-up path of the pull-upcircuit 16 is turned on.

That is, at the time point tc, the pull-up path is turned on.Consequently, the voltage at the node “a” is pulled up to the high logiclevel (i.e., Vcc) quickly, and the voltage at the node “b” is decreasedto the low logic level (i.e., 0V) quickly.

At the time point td, the voltage at the node “a” has the high logiclevel (i.e., Vcc) and the voltage at the node “b” has the low logiclevel (i.e., 0V). Consequently, the pull-up path of the pull-up circuit16 is turned off again. The arbitrating circuit 20 is not in themetastable state. The transistors m1 and m4 are turned on. Thetransistors m2 and m3 are turned off. Consequently, the acknowledgingsignal ACKa is activated (i.e., 0V), and the acknowledging signal ACKbis inactivated (i.e., Vcc).

As mentioned in FIG. 2D, the pull-up path of the pull-up circuit 16 istemporarily turned on when both of the request signals REQa and REQb areactivated (i.e., 0V). Under this circumstance, the voltage at the node“a” has the high logic level (i.e., Vcc), and the voltage at the node“b” has the low logic level (i.e., 0V). Consequently, the acknowledgingsignal ACKa is activated (i.e., 0V), and the acknowledging signal ACKbis inactivated (i.e., Vcc).

In the above two embodiments, the low logic level (i.e., 0V) indicatesthat the signal is activated, and the high level (i.e., Vcc) indicatesthat the signal is inactivated. It is noted that numerous modificationsand alterations may be made while retaining the teachings of theinvention. For example, in another embodiment, the high level (i.e.,Vcc) indicates that the signal is activated and the low logic level(i.e., 0V) indicates that the signal is inactivated.

FIG. 3A is a schematic circuit diagram illustrating an arbitratingcircuit according to a third embodiment of the present invention. FIG.3B is a schematic circuit diagram illustrating an exemplary pull-downcircuit used in the arbitrating circuit of FIG. 3A. FIG. 3C is aschematic circuit diagram illustrating another exemplary pull-downcircuit used in the arbitrating circuit of FIG. 3A. FIG. 3D is aschematic timing waveform diagram illustrating associated signals of thearbitrating circuit of FIG. 3A.

As shown in FIG. 3A, the arbitrating circuit 30 comprises a first NANDgate 32, a second NAND gate 34, four transistors M1˜M4 and a pull-downcircuit 36. The transistors M1 and M3 are P-type transistors, and thetransistors M2 and M4 are N-type transistors.

A first input terminal of the first NAND gate 32 receives the requestsignal REQa. A second input terminal of the first NAND gate 32 isconnected with the node “b”. An output terminal of the first NAND gate32 is connected with the node “a”. A first input terminal of the secondNAND gate 34 receives the request signal REQb. A second input terminalof the second NAND gate 34 is connected with the node “a”. An outputterminal of the second NAND gate 34 is connected with the node “b”.

The source terminal of the transistor M1 is connected with the node “b”.The gate terminal of the transistor M1 is connected with the node “a”.The drain terminal of the transistor M1 generates an acknowledge signalACKa. The source terminal of the transistor M2 is connected with aground terminal GND. The gate terminal of the transistor M2 is connectedwith the node “a”. The drain terminal of the transistor M2 is connectedwith the drain terminal of the transistor M1. The voltage of the groundterminal GND is equal to 0V, indicating the low logic level. The voltageof the high logic level is equal to the supply voltage Vcc.

The source terminal of the transistor M3 is connected with the node “a”.The gate terminal of the transistor M3 is connected with the node “b”.The drain terminal of the transistor M3 generates an acknowledge signalACKb. The source terminal of the transistor M4 is connected with theground terminal GND. The gate terminal of the transistor M4 is connectedwith the node “b”. The drain terminal of the transistor M4 is connectedwith the drain terminal of the transistor M3.

In this embodiment, the pull-down circuit 36 is connected with the node“a”, the node “b”, the first input terminal of the first NAND gate 32and the first input terminal of the second NAND gate 34. The pull-downcircuit 36 is operated according to the voltage at the node “a”, thevoltage at the node “b”, the request signal REQa and the request signalREQb. In case that both of the request signals REQa and REQb have thehigh logic level, the pull-down path of the pull-down circuit 36 istemporarily turned on. Under this circumstance, the voltage at the node“a” is pulled down to the 0V.

In the example of FIG. 3B, the pull-down circuit 36 comprises fourtransistors, which are connected between the node “a” and the groundterminal GND in series. The gate terminals of the four transistors areconnected with the node “a”, the node “b”, the first input terminal ofthe first NAND gate 32 and the first input terminal of the second NANDgate 34, respectively.

Please refer to FIG. 3B again. The pull-down circuit 36 comprises thefour transistors Ma, Mb, Mc and Md. The transistors Ma, Mb, Mc and Mdare serially connected between the node “a” and the ground terminal GNDto define the pull-down path. The transistors Ma, Mb, Mc and Md areN-type transistors. The drain terminal and the gate terminal of thetransistor Ma are connected with the node “a”. The drain terminal of thetransistor Mb is connected with the source terminal of the transistorMa. The gate terminal of the transistor Mb is connected with the node“b”. The drain terminal of the transistor Mc is connected with thesource terminal of the transistor Mb. The gate terminal of thetransistor Mc receives the request signal REQa. The drain terminal ofthe transistor Md is connected with the source terminal of thetransistor Mc. The gate terminal of the transistor Md receives therequest signal REQb. The source terminal of the transistor Md isconnected with the ground terminal GND.

It is noted that the signals to be received by the four gate terminalsof the pull-down circuit 36 may be varied according to the practicalrequirements. For example, in another embodiment, the gate terminals ofthe transistors Ma, Mb, Mc and Md are connected with node “b”, the node“a”, the request signal REQb and the request signal REQa, respectively.

In the example of FIG. 3C, the pull-down circuit 36 comprises an ANDgate 38 and three transistors. The two input terminals of the AND gate38 receive the request signals REQa and REQb, respectively. The threetransistors are connected between the node “a” and the ground terminalGND in series. The gate terminals of the three transistors are connectedwith the node “a”, the node “b” and the output terminal of the AND gate38, respectively.

Please refer to FIG. 3C again. The pull-down circuit 36 comprises thethree transistors Me, Mf and Mg and the AND gate 38. The transistors Me,Mf and Mg are N-type transistors. The transistors Me, Mf and Mg areserially connected between the node “a” and the ground terminal GND todefine the pull-down path. The drain terminal and the gate terminal ofthe transistor Me are connected with the node “a”. The drain terminal ofthe transistor Mf is connected with the source terminal of thetransistor Me. The gate terminal of the transistor Mf is connected withthe node “b”. The drain terminal of the transistor Mg is connected withthe source terminal of the transistor Mf. The source terminal of thetransistor Mg is connected with the ground terminal GND. The two inputterminals of the AND gate 38 receive the request signals REQa and REQb.The output terminal of the AND gate 38 is connected with the gateterminal of the transistor Mg.

It is noted that the signals to be received by the three gate terminalsof the pull-down circuit 36 may be varied according to the practicalrequirements. For example, in another embodiment, the gate terminals ofthe transistors Me, Mf and Me are connected with node “b”, the node “a”and the output terminal of the AND gate 38, respectively.

The examples of the pull-down circuit 36 as shown in FIGS. 3B and 3C arepresented herein for purpose of illustration and description only. It isapparent to those ordinarily skilled in the art that numerousmodifications and alterations may be made while retaining the teachingsof the invention.

In the arbitrating circuit 30, the high level (i.e., Vcc) indicates thatthe signal is activated, and the low logic level (i.e., 0V) indicatesthat the signal is inactivated.

In case that the request signals REQa and REQb are both inactivated(i.e., 0V), the voltages at the node “a” and the node “b” have the highlogic level (i.e., Vcc). The transistors M2 and M4 are turned on. Thetransistors M1 and M3 are turned off. That is, the pull-down path of thepull-down circuit 36 is turned off. Consequently, the acknowledgingsignals ACKa and ACKb are inactivated (i.e., 0V).

In case that the request signal REQa is activated (i.e., Vcc) and therequest signal REQb is inactivated (i.e., 0V), the voltage at the node“a” has the low logic level (i.e., 0V) and the voltage at the node “b”has the high logic level (i.e., Vcc). The transistors M1 and M4 areturned on. The transistors M2 and M3 are turned off. That is, thepull-down path of the pull-down circuit 36 is turned off. Consequently,the acknowledging signal ACKa is activated (i.e., Vcc), and theacknowledging signal ACKb is inactivated (i.e., 0V).

In case that the request signal REQa is inactivated (i.e., 0V) and therequest signal REQb is activated (i.e., Vcc), the voltage at the node“a” has the high logic level (i.e., Vcc) and the voltage at the node “b”has the low logic level (i.e., 0V). The transistors M2 and M3 are turnedon. The transistors M1 and M4 are turned off. That is, the pull-downpath of the pull-down circuit 36 is turned off. Consequently, theacknowledging signal ACKa is inactivated (i.e., 0V), and theacknowledging signal ACKb is activated (i.e., Vcc).

As mentioned above, the arbitrating circuit 30 is capable of determiningwhether the acknowledging signal ACKa or the acknowledging signal ACKbis activated. If the request signal REQa is activated earlier, theacknowledging signal ACKa is activated and the acknowledging signal ACKbis inactivated. Whereas, if the request signal REQb is activatedearlier, the acknowledging signal ACKb is activated and theacknowledging signal ACKa is inactivated. Moreover, if the requestsignals REQa and REQb are not simultaneously activated, the pull-downpath of the pull-down circuit 36 is turned off.

In this embodiment, if the request signals REQa and REQb of thearbitrating circuit 30 are activated simultaneously, the acknowledgingsignal ACKa is activated, and the acknowledging signal ACKb isinactivated. The reasons will be described as follows in more details.

Please refer to FIG. 3D. At the time point te, the request signals REQaand REQb are activated simultaneously (i.e., Vcc). Meanwhile, thearbitrating circuit 30 is in a metastable state (MS).

In the metastable state, the request signals REQa and REQb have the highlogic level (i.e., 0V), and the voltages at the node “a” and the node“b” are in the range between the high logic level and the low logiclevel. Consequently, the transistors Ma, Mb, Mc and Md of the pull-downcircuit 36 as shown in FIG. 3B are turned on. That is, the pull-downpath of the pull-down circuit 36 is turned on. Similarly, in themetastable state, the transistors Me, Mf and Mg of the pull-down circuit36 as shown in FIG. 3C are turned on. That is, the pull-down path of thepull-down circuit 36 is turned on.

That is, at the time point te, the pull-down path is turned on.Consequently, the voltage at the node “a” is pulled down to the lowlogic level (i.e., 0V) quickly, and the voltage at the node “b” isincreased to the high logic level (i.e., Vcc) quickly.

At the time point tf, the voltage at the node “a” has the low logiclevel (i.e., 0V) and the voltage at the node “b” has the high logiclevel (i.e., Vcc). Consequently, the pull-down path of the pull-downcircuit 36 is turned off again. The arbitrating circuit 30 is not in themetastable state. The transistors M1 and M4 are turned on. Thetransistors M2 and M3 are turned off. Consequently, the acknowledgingsignal ACKa is activated (i.e., Vcc), and the acknowledging signal ACKbis inactivated (i.e., 0V).

As mentioned in FIG. 3D, the pull-down path of the pull-down circuit 36is temporarily turned on when both of the request signals REQa and REQbare activated (i.e., Vcc). Under this circumstance, the voltage at thenode “a” has the low logic level (i.e., 0V), and the voltage at the node“b” has the high logic level (i.e., Vcc). Consequently, theacknowledging signal ACKa is activated (i.e., Vcc), and theacknowledging signal ACKb is inactivated (i.e., 0V).

From the above descriptions, the present invention provides anarbitrating circuit. If the two request signals REQa and REQb receivedby the arbitrating circuit are activated simultaneously, the pull-upcircuit or the pull-down circuit is used to allow the arbitratingcircuit to be departed from the metastable state. Moreover, theacknowledging signal ACKa is activated, and the acknowledging signalACKb is inactivated.

While the invention has been described in terms of what is presentlyconsidered to be the most practical and preferred embodiments, it is tobe understood that the invention needs not be limited to the disclosedembodiment. On the contrary, it is intended to cover variousmodifications and similar arrangements included within the spirit andscope of the appended claims which are to be accorded with the broadestinterpretation so as to encompass all such modifications and similarstructures.

What is claimed is:
 1. An arbitrating circuit, comprising: a first NORgate, wherein a first input terminal of the first NOR gate receives afirst request signal, a second input terminal of the first NOR gate isconnected with a first node, and an output terminal of the first NORgate is connected with a second node; a second NOR gate, wherein a firstinput terminal of the second NOR gate receives a second request signal,a second input terminal of the second NOR gate is connected with thesecond node, and an output terminal of the second NOR gate is connectedwith the first node; a first transistor, wherein a source terminal ofthe first transistor is connected with the first node, a gate terminalof the first transistor is connected with the second node, and a drainterminal of the first transistor generates a first acknowledging signal;a second transistor, wherein a source terminal of the second transistoris connected with a supply voltage, a gate terminal of the secondtransistor is connected with the second node, and a drain terminal ofthe second transistor is connected with the drain terminal of the firsttransistor; a third transistor, wherein a source terminal of the thirdtransistor is connected with the second node, a gate terminal of thethird transistor is connected with the first node, and a drain terminalof the third transistor generates a second acknowledging signal; afourth transistor, wherein a source terminal of the fourth transistor isconnected with the supply voltage, a gate terminal of the fourthtransistor is connected with the first node, and a drain terminal of thefourth transistor is connected with the drain terminal of the thirdtransistor; and a pull-up circuit connected with the first node, thesecond node, the first input terminal of the first NOR gate and thefirst input terminal of the second NOR gate, wherein if both of thefirst request signal and the second request signal have a low logiclevel, a voltage at the second node is pulled up to a high logic levelby the pull-up circuit.
 2. The arbitrating circuit as claimed in claim1, wherein the pull-up circuit comprises four transistors, which areconnected between the second node and the supply voltage in series,wherein gate terminals of the four transistors of the pull-up circuitare connected with the first node, the second node, the first inputterminal of the first NOR gate and the first input terminal of thesecond NOR gate, respectively.
 3. The arbitrating circuit as claimed inclaim 2, wherein the four transistors of the pull-up circuit comprises:a fifth transistor including a drain terminal connected with the secondnode, a gate terminal connected with the second node and a sourceterminal; a sixth transistor including a drain terminal connected withthe source terminal of the fifth transistor, a gate terminal connectedwith the first node, and a source terminal; a seventh transistorincluding a drain terminal connected with the source terminal of thesixth transistor, a gate terminal connected with the first inputterminal of the second NOR gate, and a source terminal; and an eighthtransistor including a drain terminal connected with the source terminalof the seventh transistor, a gate terminal connected with the firstinput terminal of the first NOR gate, and a source terminal connectedwith the supply voltage.
 4. The arbitrating circuit as claimed in claim1, wherein the pull-up circuit comprises: an OR gate including a firstinput terminal receiving the first request signal, a second inputterminal receiving the second request signal and an output terminal; andthree transistors, which are connected between the second node and thesupply voltage in series, wherein gate terminals of the threetransistors of the pull-up circuit are connected with the first node,the second node and the output terminal of the OR gate, respectively. 5.The arbitrating circuit as claimed in claim 4, wherein the threetransistors of the pull-up circuit comprises: a ninth transistorincluding a drain terminal connected with the second node, a gateterminal connected with the second node and a source terminal; a tenthtransistor including a drain terminal connected with the source terminalof the ninth transistor, a gate terminal connected with the first node,and a source terminal; and an eleventh transistor including a drainterminal connected with the source terminal of the tenth transistor, agate terminal connected with the output terminal of the OR gate, and asource terminal connected with the supply voltage.
 6. An arbitratingcircuit, comprising: a first NAND gate, wherein a first input terminalof the first NAND gate receives a first request signal, a second inputterminal of the first NAND gate is connected with a first node, and anoutput terminal of the first NAND gate is connected with a second node;a second NAND gate, wherein a first input terminal of the second NANDgate receives a second request signal, a second input terminal of thesecond NAND gate is connected with the second node, and an outputterminal of the second NAND gate is connected with the first node; afirst transistor, wherein a source terminal of the first transistor isconnected with the first node, a gate terminal of the first transistoris connected with the second node, and a drain terminal of the firsttransistor generates a first acknowledging signal; a second transistor,wherein a source terminal of the second transistor is connected with aground terminal, a gate terminal of the second transistor is connectedwith the second node, and a drain terminal of the second transistor isconnected with the drain terminal of the first transistor; a thirdtransistor, wherein a source terminal of the third transistor isconnected with the second node, a gate terminal of the third transistoris connected with the first node, and a drain terminal of the thirdtransistor generates a second acknowledging signal; a fourth transistor,wherein a source terminal of the fourth transistor is connected with theground terminal, a gate terminal of the fourth transistor is connectedwith the first node, and a drain terminal of the fourth transistor isconnected with the drain terminal of the third transistor; and apull-down circuit connected with the first node, the second node, thefirst input terminal of the first NAND gate and the first input terminalof the second NAND gate, wherein if both of the first request signal andthe second request signal have a high logic level, a voltage at thesecond node is pulled down to a low logic level by the pull-downcircuit.
 7. The arbitrating circuit as claimed in claim 6, wherein thepull-down circuit comprises four transistors, which are connectedbetween the second node and the ground terminal in series, wherein gateterminals of the four transistors of the pull-down circuit are connectedwith the first node, the second node, the first input terminal of thefirst NAND gate and the first input terminal of the second NAND gate,respectively.
 8. The arbitrating circuit as claimed in claim 7, whereinthe four transistors of the pull-down circuit comprises: a fifthtransistor including a drain terminal connected with the second node, agate terminal connected with the second node and a source terminal; asixth transistor including a drain terminal connected with the sourceterminal of the fifth transistor, a gate terminal connected with thefirst node and a source terminal; a seventh transistor including a drainterminal connected with the source terminal of the sixth transistor, agate terminal connected with the first input terminal of the first NANDgate and a source terminal; and an eighth transistor including a drainterminal connected with the source terminal of the seventh transistor, agate terminal connected with the first input terminal of the second NANDgate and a source terminal connected with the ground terminal.
 9. Thearbitrating circuit as claimed in claim 6, wherein the pull-down circuitcomprises: an AND gate including a first input terminal receiving thefirst request signal, a second input terminal receiving the secondrequest signal and an output terminal; and three transistors, which areconnected between the second node and the ground terminal in series,wherein gate terminals of the three transistors of the pull-down circuitare connected with the first node, the second node and the outputterminal of the AND gate, respectively.
 10. The arbitrating circuit asclaimed in claim 9, wherein the three transistors of the pull-up circuitcomprises: a ninth transistor including a drain terminal connected withthe second node, a gate terminal connected with the second node and asource terminal; a tenth transistor including a drain terminal connectedwith the source terminal of the ninth transistor, a gate terminalconnected with the first node and a source terminal; and an eleventhtransistor including a drain terminal connected with the source terminalof the tenth transistor, a gate terminal connected with the outputterminal of the AND gate and a source terminal connected with the groundterminal.